I have resumed work on the FPGA implementation of the IBM 360/65. I now have access to a complete set of IBM ALD's for the 7201-02 (the FAA 9020 customized version of the 2065 CPU), and because of that, I've decided to change how I'm implementing the CPU on the FPGA. Rather than working from the diagrams in the FEMDM (which are useful, but less detailed), I am now modeling the ALD's directly, which means that the emulation will be gate-level accurate.

The problem with modeling from the FEMDM, is that the diagrams in the FEMDM are representative of the circuits found in the CPU, but not accurate enough to base a simulation on. The ALD's show the actual AND, OR, and NOT gates, and are therefore much more accurate.

One ALD (Automated Logic Diagram) sheet of schematics out of about 1300 that I need to translate into VHDL for the emulator

The XC5VLX110T FPGA has 17,280 logic slices available; 2,440 of these are taken by the PCIe interface (for I/O) and DDR2 controller (for main storage), and about 400 are taken by the shift registers to control the lamps and switches, leaving 14,440 for the CPU itself. Of the 3000+ pages of ALD's, I have identified 1315 that need to be translated into VHDL; I have completed 854 of these so far (although they still need lots of testing), and these take up around 5,200 slices. So, it's reasonable to expect that the finished CPU will occupy around 8,000-9,000 slices, which in turn means that the FPGA is very likely to be large enough for our needs.

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Manufacturer IBM
CPU Microcoded 32-bit CPU (64-bit path to core memory) implementing the System/360 architecture
Memory 1 MB Core memory (4 x 2365 Processor Storage Model 2)
Original Price Typical configuration with 1 MB memory, 1968-dollars:
Rental: US$200,000 per month (US$1,400,000 in 2014-dollars)
Buy: US$4,000,000 (US$27,000,000 in 2014-dollars)
Number known to exist 1 (in the Smithsonian Institute, non-functioning)
Introduced 1965


The Model 65 was a member of the first generation (Models 30, 40, 50, 65, 75) of the famous IBM System/360 series of mainframes. As the biggest of the microcoded System/360's, it sat at the mid high-end of the spectrum.

All that remains now of this once great machine, which cost around 4 million dollars back in 1968 (equivalent of 27 million of today's dollars), is the operator's console panel.

These console panels were used to control and monitor di fferent parts of (mainly) the CPU.

I'm connecting this console panel to a simulator of the Model 65 CPU. Progress on that project can be found here. Read about its acquisition here: IBM 360 Console Panel Arrived.

I realised that I'd need some extra hardware to connect the PCIe card to the console panel. The I/O pins on the Xilinx board operate at either 2.8 or 3.3 volts, and my console panel circuitry operates at 5 volts. So, what I need is some level shifters. I got four of these 4-way level shifters, and put them on a piece of veroboard with connectors for the Xilinx board and a 50-pin ribbon cable.

The 50-pin ribbon cable terminates in an HD50 connector (commonly used for narrow SCSI applications) on a PCI bracket. The panel has been fitted with the same connector, so a SCSI cable can be used as an interconnect between the PC and the panel.

This file pcie360_0_1_20120413.zip contains the VHDL code for the FPGA implementation of the 2065 emulator (incomplete, but capable of some elementary operations from the console panel). Here's the description from the top-level file (pcie360.vhd):

This is the design for an FPGA implementation of an IBM 2065 CPU emulator. As I have insufficient documentation on the IBM 2065, and because I don't have a copy of the ROS contents of the 2065, this is really an IBM 7201-2 CE emulator with 7201-specific bits stripped out.

Major subcomponents are:

  • cpu - actual CPU emulation
  • blinken - interface to an IBM 2065 console panel w/shift registers
  • corememory - 256 KB of main memory (dual-ported between cpu and ioce)
  • ioce - interface for the IOCE emulator running on the PC
  • pcie - PCIE endblock to communicate with the PC (*)

This design is intended to be implemented on the Xilinx ML509 / XUPV5 developer board.

(*) A Xilinx PCI Express Endpoint Core example design needs to be added for this design to work. I cannot include that here because of copyright restrictions.

Over the past few weeks, I've decided that there are a two things I don't like about the current 2065 emulator. These are:

  • In the real 2065, several things would happen at once every 10 ns sub-cycle. The software emulator is necessarily much more sequential;
  • The blinkenlights console doesn't get updated frequently enough.

Rather radically, I have therefore decided to change the emulator from a software emulator into a hardware emulator. Inspired by Lawrence Wilkinson's model 30 emulator on an FPGA, I'm going to implement the 2065 emulator on an FPGA as well.

The idea is to have the 2065 CPU and memory, as well as the logic to control the console panel on the FPGA board. For now, I'm not going to implement channel I/O on the FPGA, in stead, the FPGA will be interfaced with a PC running a software emulator of the channel and other I/O hardware.

The interface between the FPGA and the sioftware I/O will need to be able to support the following actions:

  • The FPGA tells the software to execute an IPL, START I/O, TEST I/O, HALT I/O or TEST CHANNEL command;
  • The software has read and write access to main memory implemented on the FPGA board;
  • The software signals interrupt status to the FPGA board;
  • The FPGA board signals interrupt completion to the FPGA board.

The interface needs to be reasonably fast and reliable. I found that FPGA development boards are available that fit into a PCIe slot. I've selected the Xilinx XUPV5 board pictured above for this project, as it has ample logic, a PCIe interface, and I/O pins that don't use exotic connectors.

Next thing to do is to build a small interface to connect the XUPV5 to the shift registers that drive the console panel.